1. Field of the Invention
The present invention relates to a video composition circuit such as a television and, more particularly, to a reduction in the circuit scale.
2. Description of the Related Art
Conventionally, when image composition or filtering is carried out in a video composition circuit such as a television, different circuits are prepared every time the composition is carried out.
Hereinafter, a conventional video composition circuit will be described.
FIG. 3 shows a conventional video composition circuit.
In FIG. 3, 301 denotes an external storage unit provided outside the video composition circuit, 302 denotes a transfer control unit for controlling transfer of data from the external storage unit 301, 303 denotes an internal storage unit provided in the video composition circuit, 304 denotes an OSD output unit for processing OSD display data outputted from the internal storage unit 303 to perform OSD output, 305 denotes a sub video output unit for processing sub video data outputted from the internal storage unit 303 to perform sub video output, 306 denotes a main video output unit for processing main video data outputted from the internal storage unit 303 to perform main video output, and 307 denotes a video output unit for combining the outputs from the OSD output unit 304, the sub video output unit 305, and the main video output unit 306 to perform video output. Further, 308 denotes, for example, a display having a digital signal input, which displays the video signal outputted from the video output unit 307. In the above-mentioned construction, the constituents other than the external storage unit 301 and the display 303 are fabricated on the same chip.
Further, an LUT (Look Up Table) circuit, for performing color conversion processing such as CLUT (Color Look Up Table) processing and gamma correction processing, is incorporated in the OSD output unit, and a DDA (Digital Differential Analysis) circuit for performing inter-pixel interpolation by digital differential analysis is incorporated in each of the main video output unit 306 and the sub video output unit 305 according to need. Further, a DDA circuit and two α composition circuits are incorporated in the main video output unit 306.
The operation of the video composition circuit constructed as described above will be described with reference to FIG. 5.
The main video data 508, the sub video data 509, and the OSD data 510 are serially and successively outputted from the external storage unit 301, respectively.
During a main video 1 transfer period 503, main video data 508 is transferred from the external storage unit 301 through the transfer control unit 302 to the internal storage unit 303, and stored as main video 1 (511) in the internal storage unit 303. Subsequently, during a main video 2 transfer period 504, another main video data 508 is transferred from the external storage unit through the transfer control unit 302 to the internal storage unit 303, and further, the main video data 508 is transferred to the main video output unit 306 and processed, and stored as data 512 after main video filtering in the internal storage circuit 303.
Next, during a sub video transfer period 505, sub video data 509 is transferred from the external storage unit 301 through the transfer control unit 302 to the internal storage unit 303, and further, the sub video data 509 is transferred to the sub video output unit 305 and processed, and the processed main video and sub video data 513 is stored in the internal storage circuit 303.
Next, during an OSD transfer period 506, OSD display data 510 is transferred from the external storage unit 301 through the transfer control unit 302 to the internal storage unit 303, and further, the OSD display data 510 is transferred to the OSD output unit 304 and processed. Furthermore, in the subsequent-stage video output unit 307, the OSD display data processed by the OSD output unit 304 and the previously processed main video and sub video data 513 are combined, thereby obtaining final output video data 514.
In the operation of the above-mentioned circuit, the processings are finally carried out in synchronization with a display period 502 which is a display speed of frames based on a horizontal sync signal 501.
Patent Document 1: Japanese Published Patent Application No. Hei. 11-352946 (Page 17, FIG. 1)